synchronous Designing

There are two generally accepted architectures for Synchronous State Machines. The first type considered is a state machine in which the outputs depend only on the current state. This is commonly known as a Moore machine. In the second type, the outputs depend on both the current state and the input variables. This is
known as a Mealy Machine

Which one is better ..?
In mealy machine,as soon as the input bit is one.. the output will become logic high.It need not go into another state.
Now let us see for Moore machine... If the incoming input bit is one it will go to another state upon the clock tick where we will take output which depends on the present state.

Mealy is fast but it is asynchronous. since the output changes as soon as the inputs change according to the logic and for any asynchronously behaving circuit will have glitches.

Comes to Moore, its output always depends on the State or nothing but registered output but not input.

Mealy always have one state lesser than compared to Moore, after all state is nothing but the flip flops condition.
Most designers goes for Moore state machine.


When it comes to Logic design .. ? 

Well, some of the designers feel that " This is an academic distinction and in general something you will pretty much never pay any attention to during logic design. As for speed, again, it is impossible to tell which one is 'faster' just by that distinction (mealy vs. moore). The remark about glitches is also not true, if the FSM is a part of a larger synchronous design there is no danger from glitches. In case the FSM outputs are going to another clock domain, glitches are still a very real problem even if you use a moore machine. you pick what is right for the design".

Transport and Inertial Delay

Delays are usually used for behavioral models to better represent signaling at their external interface.The main difference is that transport delay adds the propagation delay to the signal. How ever the inertial delay causes the pulses less than that delay to get suppressed & will not propagate these pulses to change the output.

Inertial Delay
Inertial delay.inertial delay is the one which gate ( Component ) have,that is if a gate is modeling then in real situation it has some delay to model that inertial delay is used. For example If you model an inertial delay of, say 20 ns, and then put a pulse of, say, 10ns, through the model, it will be "swallowed" and will not appear at the output. Because I/p pulse that do not exceed the propagation delay of the gate do not propagate to the O/P.
Inertial delay is the time it takes for a signal to change its value.
This is usually representative of capacitance.The continuous-assignment will create an inertial delay.
By default delay is inertial.

Transport delay
It's the time taken by signal to propagate through a net i.e through wire also known as time of flight
transport delay is the delay of a wire. if you model a transport delay of  20ns, and then put a pulse of 10ns then it will appear after delayed by the 20ns. it is simply wire delay delay will increase more and more when wire length increases means it can vary.


Nice explanation given by some of the authors

Verilog Example

http://www.angelfire.com/in/verilogfaqtechqa.html#How%20to%20model%20Transport%20and%20Inertial%20Delays%20in

VHDL example

http://www.vlsi-world.com/content/view/39/34/