synchronous Designing

There are two generally accepted architectures for Synchronous State Machines. The first type considered is a state machine in which the outputs depend only on the current state. This is commonly known as a Moore machine. In the second type, the outputs depend on both the current state and the input variables. This is
known as a Mealy Machine

Which one is better ..?
In mealy machine,as soon as the input bit is one.. the output will become logic high.It need not go into another state.
Now let us see for Moore machine... If the incoming input bit is one it will go to another state upon the clock tick where we will take output which depends on the present state.

Mealy is fast but it is asynchronous. since the output changes as soon as the inputs change according to the logic and for any asynchronously behaving circuit will have glitches.

Comes to Moore, its output always depends on the State or nothing but registered output but not input.

Mealy always have one state lesser than compared to Moore, after all state is nothing but the flip flops condition.
Most designers goes for Moore state machine.


When it comes to Logic design .. ? 

Well, some of the designers feel that " This is an academic distinction and in general something you will pretty much never pay any attention to during logic design. As for speed, again, it is impossible to tell which one is 'faster' just by that distinction (mealy vs. moore). The remark about glitches is also not true, if the FSM is a part of a larger synchronous design there is no danger from glitches. In case the FSM outputs are going to another clock domain, glitches are still a very real problem even if you use a moore machine. you pick what is right for the design".