Synchronous reset logic will synthesize to smaller flipflops, particularly if the reset is gated with logic generating the input. But in such a case the combinational logic gate count grows, So the overall gate count savings may not be that significant.
The clock works as a filter for smaller reset glitches; However, if these glitches occur near the active clock edge, the flipflop could go to metastable.
Dis adv:
Problem with synchronous reset is that synthesis tool cannot be easily distinguish the reset signal from any other data signal.
Designs that are pushing limit for datapath timing, cannot afford to have added gates and additional net delays in datapath due to logic inserted to handle synchronous resets.
Asynchronous Reset:
The biggest problem with asynchronous resets is the release, also called reset removal. Using an asynchronous reset, the designer is guaranteed not to have the reset added to that datapath.
Circuit can be reset with or without a clock present.
Dis adv:
Consider that release of the reset can occur withing one clock period, if the release of reset occured on or near the clock edge such that flipflop metastable.
Gating the clock:
Clocks are gated to reduce power dissippation. Part of a cicruit which functions only on receiving certain enable signal, need not be clocked always. In such a case to prevent the sequential element from being clocked through the enable signal is not active, clock gating is used.
To reduce metastability designers most commonly use a multiple-stage synchronizer in which two or more flipflops are cascaded to form a synchronous cicruit.
Example code:
always@( posedge clk or negedge rst_n)
if (~rst_n)
signal <= 1'b0;
else
begin // Synchronization of signal.
signal_d1 <= signal;
signal_d2 <= signal_d1;
end
Conclusion:
Every design has it own merits and demerits. There is nothing called perfect design.
Synchronous reset needs more gates it to implement and therefore it would be slow due to combinational delay.
Asynchronous reset doesnt require more gates to implement and it would be faster. But it suffers from metastability problems.
